Field of the Invention
The invention relates to a DRAM cell configuration, that is to say a memory cell configuration with dynamic random access in which a memory cell has three transistors.
In DRAM cell arrangements, use is made almost exclusively of so-called single-transistor memory cells. A single-transistor memory cell includes a read-out transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electric charge which represents a logic value (0 or 1). By driving the read-out transistor via a word line, the information can be read out via a bit line. The electric charge stored in the storage capacitor drives the bit line in this case.
Since the storage density increases from memory generation to memory generation, the required area of the single-transistor memory cell must be reduced from generation to generation. This leads to fundamental technological and physical problems. For example, despite the smaller area of the single-transistor memory cell, the storage capacitor must be able to store a minimum amount of electric charge in order thereby to be able to drive the bit line.
The problem is circumvented in an alternative DRAM cell configuration in which so-called gain cells are used as memory cells. Here, too, the information is stored in the form of an electric charge. However, the electric charge does not have to drive a bit line directly, but rather is stored in a gate electrode of a transistor and serves only to control the latter, for which purpose a very small amount of electric charge is actually sufficient.
A gain cell having three transistors is described in an article authored by M. Heshami, 1996 IEEE J., "Solid-State Circuits", Vol. 31, No. 3. The electric charge is stored in a gate electrode of a first transistor. The electric charge is stored with the aid of a second transistor. The gate electrode of the first transistor is connected to a first source/drain region of the second transistor and a second source/drain region of the second transistor is connected to a writing bit line. For the purpose of storage, a gate electrode of the second transistor is driven via a writing word line. The amount of electric charge and thus the information stored in the gate electrode of the first transistor in the process is determined by a voltage on the writing bit line. The information is read out with the aid of a third transistor. A second source/drain region of the first transistor is connected to a first source/drain region of the third transistor and a second source/drain region of the third transistor is connected to a read-out bit line. For the purpose of read-out, a gate electrode of the third transistor is driven via a read-out word line. The amount of electric charge, and thus the information, is read out via the read-out bit line.